Impacts of bends and ground return vias on interconnects for high speed GHz designs
In the past only critical clock circuits are running at high speed but this is no longer true in today high-speed digital...
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Main Authors: | , , |
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Other Authors: | |
Format: | Conference or Workshop Item |
Language: | English |
Published: |
2010
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Subjects: | |
Online Access: | https://hdl.handle.net/10356/91031 http://hdl.handle.net/10220/6386 |
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Institution: | Nanyang Technological University |
Language: | English |
Summary: | In the past only critical clock circuits are running at
high speed but this is no longer true in today high-speed digital
design world. Most of the digital traces on board are running at
speed in excess of 200 MHz and drivers output with rise time less
than 1 ns. Due to constraints of board size and highly complex
designs, trace bends and inter-layer transitions through vias are
unavoidable. This paper carries out a comprehensive study on
the impacts of bends and ground return vias optimisation on
signal integrity performance using a full-wave electromagnetic
simulator. (CST Microwave Studio). This study will provide
high-speed digital designers an in-depth assessment of these
effects in high-speed GHz applications so that some design guides
to avoid these effects can be established. |
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