Impacts of bends and ground return vias on interconnects for high speed GHz designs
In the past only critical clock circuits are running at high speed but this is no longer true in today high-speed digital...
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sg-ntu-dr.10356-910312020-03-07T13:24:46Z Impacts of bends and ground return vias on interconnects for high speed GHz designs Chang, Richard Weng Yew See, Kye Yak Tan, Yang Long School of Electrical and Electronic Engineering Asia-Pacific Symposium on Electromagnetic Compatibility and International Zurich Symposium on Electromagnetic Compatibility (19th : 2008 : Singapore) Guided Systems Division, DSO National Laboratories DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging In the past only critical clock circuits are running at high speed but this is no longer true in today high-speed digital design world. Most of the digital traces on board are running at speed in excess of 200 MHz and drivers output with rise time less than 1 ns. Due to constraints of board size and highly complex designs, trace bends and inter-layer transitions through vias are unavoidable. This paper carries out a comprehensive study on the impacts of bends and ground return vias optimisation on signal integrity performance using a full-wave electromagnetic simulator. (CST Microwave Studio). This study will provide high-speed digital designers an in-depth assessment of these effects in high-speed GHz applications so that some design guides to avoid these effects can be established. Published version 2010-09-02T03:59:54Z 2019-12-06T17:58:29Z 2010-09-02T03:59:54Z 2019-12-06T17:58:29Z 2008 2008 Conference Paper Chang, R. W. Y., See, K. Y., & Tan, Y. L. (2008). Impacts of bends and ground return vias on interconnects for high speed GHz designs. In proceedings of the Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility: Singapore, (pp.502-505). https://hdl.handle.net/10356/91031 http://hdl.handle.net/10220/6386 10.1109/APEMC.2008.4559922 en © 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. 4 p. application/pdf |
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Nanyang Technological University |
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Singapore |
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English |
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DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging |
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DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging Chang, Richard Weng Yew See, Kye Yak Tan, Yang Long Impacts of bends and ground return vias on interconnects for high speed GHz designs |
| description |
In the past only critical clock circuits are running at
high speed but this is no longer true in today high-speed digital
design world. Most of the digital traces on board are running at
speed in excess of 200 MHz and drivers output with rise time less
than 1 ns. Due to constraints of board size and highly complex
designs, trace bends and inter-layer transitions through vias are
unavoidable. This paper carries out a comprehensive study on
the impacts of bends and ground return vias optimisation on
signal integrity performance using a full-wave electromagnetic
simulator. (CST Microwave Studio). This study will provide
high-speed digital designers an in-depth assessment of these
effects in high-speed GHz applications so that some design guides
to avoid these effects can be established. |
| author2 |
School of Electrical and Electronic Engineering |
| author_facet |
School of Electrical and Electronic Engineering Chang, Richard Weng Yew See, Kye Yak Tan, Yang Long |
| format |
Conference or Workshop Item |
| author |
Chang, Richard Weng Yew See, Kye Yak Tan, Yang Long |
| author_sort |
Chang, Richard Weng Yew |
| title |
Impacts of bends and ground return vias on interconnects for high speed GHz designs |
| title_short |
Impacts of bends and ground return vias on interconnects for high speed GHz designs |
| title_full |
Impacts of bends and ground return vias on interconnects for high speed GHz designs |
| title_fullStr |
Impacts of bends and ground return vias on interconnects for high speed GHz designs |
| title_full_unstemmed |
Impacts of bends and ground return vias on interconnects for high speed GHz designs |
| title_sort |
impacts of bends and ground return vias on interconnects for high speed ghz designs |
| publishDate |
2010 |
| url |
https://hdl.handle.net/10356/91031 http://hdl.handle.net/10220/6386 |
| _version_ |
1681046875069743104 |