Dual nanowire silicon MOSFET with silicon bridge and TaN gate
This paper demonstrates a high performance silicon nanowire mosfet built on silicon-on-insulator (SOI) platform. Stress-limiting oxidation technique was exploited for dual nanowire channel formation. To further improve the performance of the device, TaN metal gate is used instead of the conventional...
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| Main Authors: | , , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
2010
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/92303 http://hdl.handle.net/10220/6263 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | This paper demonstrates a high performance silicon nanowire mosfet built on silicon-on-insulator (SOI) platform. Stress-limiting oxidation technique was exploited for dual nanowire channel formation. To further improve the performance of the device, TaN metal gate is used instead of the conventional polysilicon gate. The thin silicon bridge between the two nanowires provides a small boost in the drive current, without degrading the short channel performance. The novel structures are able to achieve excellent electrical performances, high drive current of
927 μA/μm for p-channel and 554 μA/μm for n-channel, near ideal subthreshold slope (SS), and low drain-induced barrier lowering (DIBL). |
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