Dual nanowire silicon MOSFET with silicon bridge and TaN gate

This paper demonstrates a high performance silicon nanowire mosfet built on silicon-on-insulator (SOI) platform. Stress-limiting oxidation technique was exploited for dual nanowire channel formation. To further improve the performance of the device, TaN metal gate is used instead of the conventional...

Full description

Saved in:

Bibliographic Details
Main Authors:	Theng, A. L., Goh, Wang Ling, Ng, C. M., Chan, L., Lo, Guo-Qiang
Other Authors:	School of Electrical and Electronic Engineering
Format:	Article
Language:	English
Published:	2010
Subjects:	DRNTU::Engineering::Electrical and electronic engineering
Online Access:	https://hdl.handle.net/10356/92303 http://hdl.handle.net/10220/6263
Tags:	Add Tag No Tags, Be the first to tag this record!
Institution:	Nanyang Technological University
Language:	English

id	sg-ntu-dr.10356-92303
record_format	dspace
spelling	sg-ntu-dr.10356-923032020-03-07T14:02:38Z Dual nanowire silicon MOSFET with silicon bridge and TaN gate Theng, A. L. Goh, Wang Ling Ng, C. M. Chan, L. Lo, Guo-Qiang School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering This paper demonstrates a high performance silicon nanowire mosfet built on silicon-on-insulator (SOI) platform. Stress-limiting oxidation technique was exploited for dual nanowire channel formation. To further improve the performance of the device, TaN metal gate is used instead of the conventional polysilicon gate. The thin silicon bridge between the two nanowires provides a small boost in the drive current, without degrading the short channel performance. The novel structures are able to achieve excellent electrical performances, high drive current of 927 μA/μm for p-channel and 554 μA/μm for n-channel, near ideal subthreshold slope (SS), and low drain-induced barrier lowering (DIBL). Published version 2010-05-05T06:40:42Z 2019-12-06T18:21:01Z 2010-05-05T06:40:42Z 2019-12-06T18:21:01Z 2008 2008 Journal Article Theng, A. L., Goh, W. L., Ng, C. M., Chan, L. & Lo, G. Q. (2008). Dual Nanowire Silicon MOSFET with Silicon Bridge and TaN Gate. IEEE Transactions on Nanotechnology. 7(6), 795-799. 1536-125X https://hdl.handle.net/10356/92303 http://hdl.handle.net/10220/6263 10.1109/TNANO.2008.917845 en IEEE transactions on nanotechnology © 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. 5 p. application/pdf
institution	Nanyang Technological University
building	NTU Library
country	Singapore
collection	DR-NTU
language	English
topic	DRNTU::Engineering::Electrical and electronic engineering
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering Theng, A. L. Goh, Wang Ling Ng, C. M. Chan, L. Lo, Guo-Qiang Dual nanowire silicon MOSFET with silicon bridge and TaN gate
description	This paper demonstrates a high performance silicon nanowire mosfet built on silicon-on-insulator (SOI) platform. Stress-limiting oxidation technique was exploited for dual nanowire channel formation. To further improve the performance of the device, TaN metal gate is used instead of the conventional polysilicon gate. The thin silicon bridge between the two nanowires provides a small boost in the drive current, without degrading the short channel performance. The novel structures are able to achieve excellent electrical performances, high drive current of 927 μA/μm for p-channel and 554 μA/μm for n-channel, near ideal subthreshold slope (SS), and low drain-induced barrier lowering (DIBL).
author2	School of Electrical and Electronic Engineering
author_facet	School of Electrical and Electronic Engineering Theng, A. L. Goh, Wang Ling Ng, C. M. Chan, L. Lo, Guo-Qiang
format	Article
author	Theng, A. L. Goh, Wang Ling Ng, C. M. Chan, L. Lo, Guo-Qiang
author_sort	Theng, A. L.
title	Dual nanowire silicon MOSFET with silicon bridge and TaN gate
title_short	Dual nanowire silicon MOSFET with silicon bridge and TaN gate
title_full	Dual nanowire silicon MOSFET with silicon bridge and TaN gate
title_fullStr	Dual nanowire silicon MOSFET with silicon bridge and TaN gate
title_full_unstemmed	Dual nanowire silicon MOSFET with silicon bridge and TaN gate
title_sort	dual nanowire silicon mosfet with silicon bridge and tan gate
publishDate	2010
url	https://hdl.handle.net/10356/92303 http://hdl.handle.net/10220/6263
_version_	1681047250455756800

Dual nanowire silicon MOSFET with silicon bridge and TaN gate

Similar Items