Dual nanowire silicon MOSFET with silicon bridge and TaN gate

• Main Authors: Theng, A. L., Goh, Wang Ling, Ng, C. M., Chan, L., Lo, Guo-Qiang
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/92303; http://hdl.handle.net/10220/6263
• Institution: Nanyang Technological University

This paper demonstrates a high performance silicon nanowire mosfet built on silicon-on-insulator (SOI) platform. Stress-limiting oxidation technique was exploited for dual nanowire channel formation. To further improve the performance of the device, TaN metal gate is used instead of the conventional...