Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity

• Main Authors: Yu, Hao, Ho, Joanna, He, Lei
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2012
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/94215; http://hdl.handle.net/10220/8745
• Institution: Nanyang Technological University

The existing work on via allocation in 3D ICs ignores power/ground vias’ ability to simultaneously reduce voltage bounce and remove heat. This paper develops the first in-depth study on the allocation of power/ground vias in 3D ICs with simultaneous consideration of power and thermal integrity. By identifying principal ports and parameters, effective electrical and thermal macromodels are employed to provide dynamic power and thermal integrity as well as sensitivity with respect to via density. With the use of sensitivity, an efficient via allocation simultaneously driven by power and thermal integrity is developed. Experiments show that compared to sequential power and thermal optimization using static integrity, sequential optimization using the dynamic integrity reduces non-signal vias by up to 18%, and simultaneous optimization using dynamic integrity further reduces non-signal vias by up to 45.5%.