Effect of copper TSV annealing on via protrusion for TSV wafer fabrication

• Main Authors: Heryanto, A., Putra, W. N., Trigg, Alastair David, Gao, S., Kwon, W. S., Che, Faxing, Ang, X. F., Wei, J., Made, Riko I., Gan, Chee Lip, Pey, Kin Leong
• Other Authors: School of Materials Science & Engineering
• Format: Article
• Language: English
• Published: 2012
• Subjects: DRNTU::Engineering::Materials
• Online Access: https://hdl.handle.net/10356/94515; http://hdl.handle.net/10220/8698
• Institution: Nanyang Technological University

Three-dimensional (3D) integrated circuit (IC) technologies are receiving increasing attention due to their capability to enhance microchip function and performance. While current efforts are focused on the 3D process development, adequate reliability of copper (Cu) through-silicon vias (TSVs) is essential for commercial high-volume manufacturing. Annealing a silicon device with copper TSVs causes high stresses in the copper and may cause a “pumping” phenomenon in which copper is forced out of the blind TSV to form a protrusion. This is a potential threat to the back-end interconnect structure, particularly for low-κ materials, since it can lead to cracking or delamination. In this work, we studied the phenomenon of Cu protrusion and microstructural changes during thermal annealing of a TSV wafer. The extruded Cu-TSV was observed using scanning electron microscopy (SEM), 3D profilometry, and atomic force microscopy (AFM). The electron backscatter diffraction (EBSD) technique was employed to study the grain orientation of Cu-TSV and evolution of the grain size as a function of annealing temperature. The elastic modulus and yield stress of copper were characterized using nanoindentation. A model for Cu protrusion is proposed to provide insight into the failure mechanism. The results help to solve a key TSV-related manufacturing yield and reliability challenge by enabling high-throughput TSV fabrication for 3D IC integration.