Analysis and design of 60-GHz SPDT switch in 130-nm CMOS
This paper proposes a new 60-GHz single-pole-double-throw (SPDT) switch. It is designed in a 1.2-V 130-nm bulk CMOS and has a small core area of 222 μm × 92 μm. The switch exhibits measured insertion loss of 1.7 dB, isolation of 22 dB, input return loss of 20 dB, output return loss of 14 dB, and sim...
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| Main Authors: | , , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
2013
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/96174 http://hdl.handle.net/10220/11418 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | This paper proposes a new 60-GHz single-pole-double-throw (SPDT) switch. It is designed in a 1.2-V 130-nm bulk CMOS and has a small core area of 222 μm × 92 μm. The switch exhibits measured insertion loss of 1.7 dB, isolation of 22 dB, input return loss of 20 dB, output return loss of 14 dB, and simulated power-handling capability of 13.8 dBm at 60 GHz. The proposed SPDT switch demonstrates such superior performances and consumes a much smaller die area to those of other SPDT switches, and therefore has potential to be used in highly integrated 60-GHz CMOS radios. |
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