Analysis and design of 60-GHz SPDT switch in 130-nm CMOS
This paper proposes a new 60-GHz single-pole-double-throw (SPDT) switch. It is designed in a 1.2-V 130-nm bulk CMOS and has a small core area of 222 μm × 92 μm. The switch exhibits measured insertion loss of 1.7 dB, isolation of 22 dB, input return loss of 20 dB, output return loss of 14 dB, and sim...
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sg-ntu-dr.10356-961742020-03-07T14:02:36Z Analysis and design of 60-GHz SPDT switch in 130-nm CMOS He, Jin Xiong, Yong-Zhong Zhang, Yue Ping School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering This paper proposes a new 60-GHz single-pole-double-throw (SPDT) switch. It is designed in a 1.2-V 130-nm bulk CMOS and has a small core area of 222 μm × 92 μm. The switch exhibits measured insertion loss of 1.7 dB, isolation of 22 dB, input return loss of 20 dB, output return loss of 14 dB, and simulated power-handling capability of 13.8 dBm at 60 GHz. The proposed SPDT switch demonstrates such superior performances and consumes a much smaller die area to those of other SPDT switches, and therefore has potential to be used in highly integrated 60-GHz CMOS radios. 2013-07-15T06:18:52Z 2019-12-06T19:26:36Z 2013-07-15T06:18:52Z 2019-12-06T19:26:36Z 2012 2012 Journal Article He, J., Xiong, Y.-Z., & Zhang, Y. P. (2012). Analysis and Design of 60-GHz SPDT Switch in 130-nm CMOS. IEEE Transactions on Microwave Theory and Techniques, 60(10), 3113-3119. https://hdl.handle.net/10356/96174 http://hdl.handle.net/10220/11418 10.1109/TMTT.2012.2211380 en IEEE transactions on microwave theory and techniques © 2012 IEEE. |
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DRNTU::Engineering::Electrical and electronic engineering He, Jin Xiong, Yong-Zhong Zhang, Yue Ping Analysis and design of 60-GHz SPDT switch in 130-nm CMOS |
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This paper proposes a new 60-GHz single-pole-double-throw (SPDT) switch. It is designed in a 1.2-V 130-nm bulk CMOS and has a small core area of 222 μm × 92 μm. The switch exhibits measured insertion loss of 1.7 dB, isolation of 22 dB, input return loss of 20 dB, output return loss of 14 dB, and simulated power-handling capability of 13.8 dBm at 60 GHz. The proposed SPDT switch demonstrates such superior performances and consumes a much smaller die area to those of other SPDT switches, and therefore has potential to be used in highly integrated 60-GHz CMOS radios. |
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School of Electrical and Electronic Engineering |
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School of Electrical and Electronic Engineering He, Jin Xiong, Yong-Zhong Zhang, Yue Ping |
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Article |
author |
He, Jin Xiong, Yong-Zhong Zhang, Yue Ping |
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He, Jin |
title |
Analysis and design of 60-GHz SPDT switch in 130-nm CMOS |
title_short |
Analysis and design of 60-GHz SPDT switch in 130-nm CMOS |
title_full |
Analysis and design of 60-GHz SPDT switch in 130-nm CMOS |
title_fullStr |
Analysis and design of 60-GHz SPDT switch in 130-nm CMOS |
title_full_unstemmed |
Analysis and design of 60-GHz SPDT switch in 130-nm CMOS |
title_sort |
analysis and design of 60-ghz spdt switch in 130-nm cmos |
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2013 |
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https://hdl.handle.net/10356/96174 http://hdl.handle.net/10220/11418 |
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