Reconfiguration algorithms for degradable VLSI arrays with switch faults

Reconfiguration algorithms for degradable VLSI arrays with switch faults

The problem of reconfiguring two-dimensional VLSI arrays with faults is to find a maximum logical array without faults. The existing algorithms only consider faults associated with processing elements, and all switches and links are assumed to be fault-free. But switch faults may often occur in the...

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書目詳細資料
Main Authors:	Zhu, Yuanbo, Wu, Jigang, Lam, Siew-Kei, Srikanthan, Thambipillai
其他作者:	School of Computer Engineering
格式:	Conference or Workshop Item
語言:	English
出版:	2013
主題:	DRNTU::Engineering::Computer science and engineering
在線閱讀:	https://hdl.handle.net/10356/98212 http://hdl.handle.net/10220/12425
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!
機構:	Nanyang Technological University
語言:	English

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