Reconfiguration algorithms for degradable VLSI arrays with switch faults

• Main Authors: Zhu, Yuanbo, Wu, Jigang, Lam, Siew-Kei, Srikanthan, Thambipillai
• Other Authors: School of Computer Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Computer science and engineering
• Online Access: https://hdl.handle.net/10356/98212; http://hdl.handle.net/10220/12425
• Institution: Nanyang Technological University

The problem of reconfiguring two-dimensional VLSI arrays with faults is to find a maximum logical array without faults. The existing algorithms only consider faults associated with processing elements, and all switches and links are assumed to be fault-free. But switch faults may often occur in the...