SIMULATION OF COPPER ELECTRODEPOSITION FOR HIGH ASPECT RATIO THROUGH- SILICON VIA APPLICATIONS IN THREE- DIMENSIONAL INTEGRATED CIRCUITS

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Bibliographic Details
Main Author:	NAGARAJAN RAGHAVAN
Other Authors:	SINGAPORE-MIT ALLIANCE
Format:	Theses and Dissertations
Published:	2019
Subjects:	Accelerator Butler Volmer kinetics Copper electrodeposition Finite element simulation Inhibitor Keyhole Leveler Overpotential Through silicon via (TSV) 3D integrated circuits
Online Access:	https://scholarbank.nus.edu.sg/handle/10635/153952
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Institution:	National University of Singapore

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spelling	sg-nus-scholar.10635-1539522019-05-10T13:14:43Z SIMULATION OF COPPER ELECTRODEPOSITION FOR HIGH ASPECT RATIO THROUGH- SILICON VIA APPLICATIONS IN THREE- DIMENSIONAL INTEGRATED CIRCUITS NAGARAJAN RAGHAVAN SINGAPORE-MIT ALLIANCE GAN CHEE LIP HONGYU LI Accelerator Butler Volmer kinetics Copper electrodeposition Finite element simulation Inhibitor Keyhole Leveler Overpotential Through silicon via (TSV) 3D integrated circuits Master's MASTER OF SCIENCE IN ADVANCED MATERIALS FOR MICRO- & NANO- SYSTEMS 2019-05-10T04:54:10Z 2019-05-10T04:54:10Z 2008 Thesis NAGARAJAN RAGHAVAN (2008). SIMULATION OF COPPER ELECTRODEPOSITION FOR HIGH ASPECT RATIO THROUGH- SILICON VIA APPLICATIONS IN THREE- DIMENSIONAL INTEGRATED CIRCUITS. ScholarBank@NUS Repository. https://scholarbank.nus.edu.sg/handle/10635/153952 SMA BATCHLOAD 20190422
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
topic	Accelerator Butler Volmer kinetics Copper electrodeposition Finite element simulation Inhibitor Keyhole Leveler Overpotential Through silicon via (TSV) 3D integrated circuits
spellingShingle	Accelerator Butler Volmer kinetics Copper electrodeposition Finite element simulation Inhibitor Keyhole Leveler Overpotential Through silicon via (TSV) 3D integrated circuits NAGARAJAN RAGHAVAN SIMULATION OF COPPER ELECTRODEPOSITION FOR HIGH ASPECT RATIO THROUGH- SILICON VIA APPLICATIONS IN THREE- DIMENSIONAL INTEGRATED CIRCUITS
description	Master's
author2	SINGAPORE-MIT ALLIANCE
author_facet	SINGAPORE-MIT ALLIANCE NAGARAJAN RAGHAVAN
format	Theses and Dissertations
author	NAGARAJAN RAGHAVAN
author_sort	NAGARAJAN RAGHAVAN
title	SIMULATION OF COPPER ELECTRODEPOSITION FOR HIGH ASPECT RATIO THROUGH- SILICON VIA APPLICATIONS IN THREE- DIMENSIONAL INTEGRATED CIRCUITS
title_short	SIMULATION OF COPPER ELECTRODEPOSITION FOR HIGH ASPECT RATIO THROUGH- SILICON VIA APPLICATIONS IN THREE- DIMENSIONAL INTEGRATED CIRCUITS
title_full	SIMULATION OF COPPER ELECTRODEPOSITION FOR HIGH ASPECT RATIO THROUGH- SILICON VIA APPLICATIONS IN THREE- DIMENSIONAL INTEGRATED CIRCUITS
title_fullStr	SIMULATION OF COPPER ELECTRODEPOSITION FOR HIGH ASPECT RATIO THROUGH- SILICON VIA APPLICATIONS IN THREE- DIMENSIONAL INTEGRATED CIRCUITS
title_full_unstemmed	SIMULATION OF COPPER ELECTRODEPOSITION FOR HIGH ASPECT RATIO THROUGH- SILICON VIA APPLICATIONS IN THREE- DIMENSIONAL INTEGRATED CIRCUITS
title_sort	simulation of copper electrodeposition for high aspect ratio through- silicon via applications in three- dimensional integrated circuits
publishDate	2019
url	https://scholarbank.nus.edu.sg/handle/10635/153952
_version_	1681099318561341440

SIMULATION OF COPPER ELECTRODEPOSITION FOR HIGH ASPECT RATIO THROUGH- SILICON VIA APPLICATIONS IN THREE- DIMENSIONAL INTEGRATED CIRCUITS

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