Multi retention level STT-RAM cache designs with a dynamic refresh scheme

10.1145/2155620.2155659

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Main Authors:	Sun, Z., Bi, X., Li, H., Wong, W.-F., Ong, Z.-L., Zhu, X., Wu, W.
Other Authors:	COMPUTER SCIENCE
Format:	Conference or Workshop Item
Published:	2013
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/42188
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Institution:	National University of Singapore

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spelling	sg-nus-scholar.10635-421882015-01-08T19:06:29Z Multi retention level STT-RAM cache designs with a dynamic refresh scheme Sun, Z. Bi, X. Li, H. Wong, W.-F. Ong, Z.-L. Zhu, X. Wu, W. COMPUTER SCIENCE 10.1145/2155620.2155659 Proceedings of the Annual International Symposium on Microarchitecture, MICRO 329-338 PSMIE 2013-07-04T08:45:34Z 2013-07-04T08:45:34Z 2011 Conference Paper Sun, Z.,Bi, X.,Li, H.,Wong, W.-F.,Ong, Z.-L.,Zhu, X.,Wu, W. (2011). Multi retention level STT-RAM cache designs with a dynamic refresh scheme. Proceedings of the Annual International Symposium on Microarchitecture, MICRO : 329-338. ScholarBank@NUS Repository. <a href="https://doi.org/10.1145/2155620.2155659" target="_blank">https://doi.org/10.1145/2155620.2155659</a> 9781450310536 10724451 http://scholarbank.nus.edu.sg/handle/10635/42188 NOT_IN_WOS Scopus
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
description	10.1145/2155620.2155659
author2	COMPUTER SCIENCE
author_facet	COMPUTER SCIENCE Sun, Z. Bi, X. Li, H. Wong, W.-F. Ong, Z.-L. Zhu, X. Wu, W.
format	Conference or Workshop Item
author	Sun, Z. Bi, X. Li, H. Wong, W.-F. Ong, Z.-L. Zhu, X. Wu, W.
spellingShingle	Sun, Z. Bi, X. Li, H. Wong, W.-F. Ong, Z.-L. Zhu, X. Wu, W. Multi retention level STT-RAM cache designs with a dynamic refresh scheme
author_sort	Sun, Z.
title	Multi retention level STT-RAM cache designs with a dynamic refresh scheme
title_short	Multi retention level STT-RAM cache designs with a dynamic refresh scheme
title_full	Multi retention level STT-RAM cache designs with a dynamic refresh scheme
title_fullStr	Multi retention level STT-RAM cache designs with a dynamic refresh scheme
title_full_unstemmed	Multi retention level STT-RAM cache designs with a dynamic refresh scheme
title_sort	multi retention level stt-ram cache designs with a dynamic refresh scheme
publishDate	2013
url	http://scholarbank.nus.edu.sg/handle/10635/42188
_version_	1681082573768359936

Multi retention level STT-RAM cache designs with a dynamic refresh scheme

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