A novel test strategy for fine pitch wafer-level packaged devices

10.1109/TADVP.2007.898617

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Bibliographic Details
Main Authors:	Jayabalan, J., Rotaru, M.D., Rao, V.S., Kripesh, V., Iyer, M.K., Tay, A.A.O., Ooi, B.-L., Leong, M.-S.
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Article
Published:	2014
Subjects:	Coplanar probe ELastomer mesh substrate Multigigahertz test Wafer-level package test and characterization
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/54653
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-54653
record_format	dspace
spelling	sg-nus-scholar.10635-546532023-10-30T09:23:40Z A novel test strategy for fine pitch wafer-level packaged devices Jayabalan, J. Rotaru, M.D. Rao, V.S. Kripesh, V. Iyer, M.K. Tay, A.A.O. Ooi, B.-L. Leong, M.-S. ELECTRICAL & COMPUTER ENGINEERING MECHANICAL ENGINEERING Coplanar probe ELastomer mesh substrate Multigigahertz test Wafer-level package test and characterization 10.1109/TADVP.2007.898617 IEEE Transactions on Advanced Packaging 30 3 439-447 ITAPF 2014-06-16T09:33:23Z 2014-06-16T09:33:23Z 2007-08 Article Jayabalan, J., Rotaru, M.D., Rao, V.S., Kripesh, V., Iyer, M.K., Tay, A.A.O., Ooi, B.-L., Leong, M.-S. (2007-08). A novel test strategy for fine pitch wafer-level packaged devices. IEEE Transactions on Advanced Packaging 30 (3) : 439-447. ScholarBank@NUS Repository. https://doi.org/10.1109/TADVP.2007.898617 15213323 http://scholarbank.nus.edu.sg/handle/10635/54653 000248671200012 Scopus
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
topic	Coplanar probe ELastomer mesh substrate Multigigahertz test Wafer-level package test and characterization
spellingShingle	Coplanar probe ELastomer mesh substrate Multigigahertz test Wafer-level package test and characterization Jayabalan, J. Rotaru, M.D. Rao, V.S. Kripesh, V. Iyer, M.K. Tay, A.A.O. Ooi, B.-L. Leong, M.-S. A novel test strategy for fine pitch wafer-level packaged devices
description	10.1109/TADVP.2007.898617
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING Jayabalan, J. Rotaru, M.D. Rao, V.S. Kripesh, V. Iyer, M.K. Tay, A.A.O. Ooi, B.-L. Leong, M.-S.
format	Article
author	Jayabalan, J. Rotaru, M.D. Rao, V.S. Kripesh, V. Iyer, M.K. Tay, A.A.O. Ooi, B.-L. Leong, M.-S.
author_sort	Jayabalan, J.
title	A novel test strategy for fine pitch wafer-level packaged devices
title_short	A novel test strategy for fine pitch wafer-level packaged devices
title_full	A novel test strategy for fine pitch wafer-level packaged devices
title_fullStr	A novel test strategy for fine pitch wafer-level packaged devices
title_full_unstemmed	A novel test strategy for fine pitch wafer-level packaged devices
title_sort	novel test strategy for fine pitch wafer-level packaged devices
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/54653
_version_	1781412010949345280

A novel test strategy for fine pitch wafer-level packaged devices

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