An area-efficient shuffling scheme for AES implementation on FPGA

An area-efficient shuffling scheme for AES implementation on FPGA

10.1109/ISCAS.2013.6572405

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書目詳細資料
Main Authors:	Wang, Y., Ha, Y.
其他作者:	ELECTRICAL & COMPUTER ENGINEERING
格式:	Conference or Workshop Item
出版:	2014
在線閱讀:	http://scholarbank.nus.edu.sg/handle/10635/69285
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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