Simulation of multiple gate FinFET device gate capacitance and performance with gate length and pitch scaling

Simulation of multiple gate FinFET device gate capacitance and performance with gate length and pitch scaling

10.1109/SISPAD.2006.282883

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Bibliographic Details
Main Authors: Zhao, H., Agrawal, N., Javier, R., Rustagi, S.C., Jurczak, M., Yeo, Y.-C., Samudra, G.S.
Other Authors: ELECTRICAL & COMPUTER ENGINEERING
Format: Conference or Workshop Item
Published: 2014
Subjects:
3D simulation
Capacitance
FinFET
Multi-gate
Scaling
Online Access:http://scholarbank.nus.edu.sg/handle/10635/71782
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Institution: National University of Singapore
Description
Summary:10.1109/SISPAD.2006.282883

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