Simulation of multiple gate FinFET device gate capacitance and performance with gate length and pitch scaling
10.1109/SISPAD.2006.282883
Saved in:
Main Authors: | Zhao, H., Agrawal, N., Javier, R., Rustagi, S.C., Jurczak, M., Yeo, Y.-C., Samudra, G.S. |
---|---|
Other Authors: | ELECTRICAL & COMPUTER ENGINEERING |
Format: | Conference or Workshop Item |
Published: |
2014
|
Subjects: | |
Online Access: | http://scholarbank.nus.edu.sg/handle/10635/71782 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | National University of Singapore |
Similar Items
-
Drive-current enhancement in FinFETs using gate-induced stress
by: Tan, K.-M., et al.
Published: (2014) -
A FinFET and Tri-gate MOSFET's channel structure patterning and its influence on the device performance
by: Jagar, S., et al.
Published: (2014) -
Analysis of the effects of fringing electric field on finFET device performance and structural optimization using 3-D simulation
by: Zhao, H., et al.
Published: (2014) -
N-channel FinFETs with 25-nm gate length and Schottky-Barrier source and drain featuring Ytterbium silicide
by: Lee, R.T.P., et al.
Published: (2014) -
Random telegraph signal noise in gate-all-around Si-FinFET with ultranarrow body
by: Lim, Y.F., et al.
Published: (2014)