Simulation of multiple gate FinFET device gate capacitance and performance with gate length and pitch scaling

10.1109/SISPAD.2006.282883

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Bibliographic Details
Main Authors:	Zhao, H., Agrawal, N., Javier, R., Rustagi, S.C., Jurczak, M., Yeo, Y.-C., Samudra, G.S.
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Conference or Workshop Item
Published:	2014
Subjects:	3D simulation Capacitance FinFET Multi-gate Scaling
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/71782
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-71782
record_format	dspace
spelling	sg-nus-scholar.10635-717822024-11-09T07:32:23Z Simulation of multiple gate FinFET device gate capacitance and performance with gate length and pitch scaling Zhao, H. Agrawal, N. Javier, R. Rustagi, S.C. Jurczak, M. Yeo, Y.-C. Samudra, G.S. ELECTRICAL & COMPUTER ENGINEERING 3D simulation Capacitance FinFET Multi-gate Scaling 10.1109/SISPAD.2006.282883 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 252-255 2014-06-19T03:27:43Z 2014-06-19T03:27:43Z 2007 Conference Paper Zhao, H.,Agrawal, N.,Javier, R.,Rustagi, S.C.,Jurczak, M.,Yeo, Y.-C.,Samudra, G.S. (2007). Simulation of multiple gate FinFET device gate capacitance and performance with gate length and pitch scaling. International Conference on Simulation of Semiconductor Processes and Devices, SISPAD : 252-255. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/SISPAD.2006.282883" target="_blank">https://doi.org/10.1109/SISPAD.2006.282883</a> 1424404045 http://scholarbank.nus.edu.sg/handle/10635/71782 NOT_IN_WOS Scopus
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
topic	3D simulation Capacitance FinFET Multi-gate Scaling
spellingShingle	3D simulation Capacitance FinFET Multi-gate Scaling Zhao, H. Agrawal, N. Javier, R. Rustagi, S.C. Jurczak, M. Yeo, Y.-C. Samudra, G.S. Simulation of multiple gate FinFET device gate capacitance and performance with gate length and pitch scaling
description	10.1109/SISPAD.2006.282883
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING Zhao, H. Agrawal, N. Javier, R. Rustagi, S.C. Jurczak, M. Yeo, Y.-C. Samudra, G.S.
format	Conference or Workshop Item
author	Zhao, H. Agrawal, N. Javier, R. Rustagi, S.C. Jurczak, M. Yeo, Y.-C. Samudra, G.S.
author_sort	Zhao, H.
title	Simulation of multiple gate FinFET device gate capacitance and performance with gate length and pitch scaling
title_short	Simulation of multiple gate FinFET device gate capacitance and performance with gate length and pitch scaling
title_full	Simulation of multiple gate FinFET device gate capacitance and performance with gate length and pitch scaling
title_fullStr	Simulation of multiple gate FinFET device gate capacitance and performance with gate length and pitch scaling
title_full_unstemmed	Simulation of multiple gate FinFET device gate capacitance and performance with gate length and pitch scaling
title_sort	simulation of multiple gate finfet device gate capacitance and performance with gate length and pitch scaling
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/71782
_version_	1821207499973328896

Simulation of multiple gate FinFET device gate capacitance and performance with gate length and pitch scaling

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