Supply-voltage optimization for below-70-nm technology-node MOSFETs

• Main Authors: Wakabayashi, H., Samudra, G.S., Djomehri, I.J., Nayfeh, H., Antoniadis, D.A.
• Other Authors: ELECTRICAL & COMPUTER ENGINEERING
• Format: Article
• Published: 2014
• Subjects: CMOS; Energy-delay product; Gate delay; Power consumption; Power-supply voltage; Short-channel effect
• Online Access: http://scholarbank.nus.edu.sg/handle/10635/83117
• Institution: National University of Singapore

10.1109/66.999586