P-channel I-MOS transistor featuring silicon nano-wire with multiple-gates, strained Si1-yCy I-region, in situ doped Si 1-yCy source, and sub-5 mV/decade subthreshold swing

P-channel I-MOS transistor featuring silicon nano-wire with multiple-gates, strained Si1-yCy I-region, in situ doped Si 1-yCy source, and sub-5 mV/decade subthreshold swing

10.1109/VTSA.2008.4530781

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Bibliographic Details
Main Authors: Toh, E.-H., Wang, G.H., Weeks, D., Zhu, M., Bauer, M., Spear, J., Chan, L., Thomas, S.G., Samudra, G., Yeo, Y.-C.
Other Authors: ELECTRICAL & COMPUTER ENGINEERING
Format: Conference or Workshop Item
Published: 2014
Online Access:http://scholarbank.nus.edu.sg/handle/10635/84069
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Institution: National University of Singapore

Internet

http://scholarbank.nus.edu.sg/handle/10635/84069

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