Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implant

Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implant

10.1109/VLSIT.2008.4588620

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Bibliographic Details
Main Authors: Wang, G.H., Toh, E.-H., Wang, X., Seng, D.H.L., Tripathy, S., Osipowicz, T., Tau, K.C., Samudra, G., Yeo, Y.-C.
Other Authors: PHYSICS
Format: Conference or Workshop Item
Published: 2014
Online Access:http://scholarbank.nus.edu.sg/handle/10635/84076
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Institution: National University of Singapore
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Summary:10.1109/VLSIT.2008.4588620

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