Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implant
10.1109/VLSIT.2008.4588620
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2014
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sg-nus-scholar.10635-840762015-01-07T08:04:37Z Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implant Wang, G.H. Toh, E.-H. Wang, X. Seng, D.H.L. Tripathy, S. Osipowicz, T. Tau, K.C. Samudra, G. Yeo, Y.-C. PHYSICS ELECTRICAL & COMPUTER ENGINEERING 10.1109/VLSIT.2008.4588620 Digest of Technical Papers - Symposium on VLSI Technology 207-208 DTPTE 2014-10-07T04:48:31Z 2014-10-07T04:48:31Z 2008 Conference Paper Wang, G.H.,Toh, E.-H.,Wang, X.,Seng, D.H.L.,Tripathy, S.,Osipowicz, T.,Tau, K.C.,Samudra, G.,Yeo, Y.-C. (2008). Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implant. Digest of Technical Papers - Symposium on VLSI Technology : 207-208. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/VLSIT.2008.4588620" target="_blank">https://doi.org/10.1109/VLSIT.2008.4588620</a> 9781424418053 07431562 http://scholarbank.nus.edu.sg/handle/10635/84076 000259116200078 Scopus |
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National University of Singapore |
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NUS Library |
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Singapore |
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ScholarBank@NUS |
| description |
10.1109/VLSIT.2008.4588620 |
| author2 |
PHYSICS |
| author_facet |
PHYSICS Wang, G.H. Toh, E.-H. Wang, X. Seng, D.H.L. Tripathy, S. Osipowicz, T. Tau, K.C. Samudra, G. Yeo, Y.-C. |
| format |
Conference or Workshop Item |
| author |
Wang, G.H. Toh, E.-H. Wang, X. Seng, D.H.L. Tripathy, S. Osipowicz, T. Tau, K.C. Samudra, G. Yeo, Y.-C. |
| spellingShingle |
Wang, G.H. Toh, E.-H. Wang, X. Seng, D.H.L. Tripathy, S. Osipowicz, T. Tau, K.C. Samudra, G. Yeo, Y.-C. Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implant |
| author_sort |
Wang, G.H. |
| title |
Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implant |
| title_short |
Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implant |
| title_full |
Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implant |
| title_fullStr |
Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implant |
| title_full_unstemmed |
Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implant |
| title_sort |
performance enhancement schemes featuring lattice mismatched s/d stressors concurrently realized on cmos platform: e-sigesn s/d for pfets by sn+ implant and sic s/d for nfets by c+ implant |
| publishDate |
2014 |
| url |
http://scholarbank.nus.edu.sg/handle/10635/84076 |
| _version_ |
1681089552684417024 |