Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implant
10.1109/VLSIT.2008.4588620
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| Main Authors: | , , , , , , , , |
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| Other Authors: | |
| Format: | Conference or Workshop Item |
| Published: |
2014
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| Online Access: | http://scholarbank.nus.edu.sg/handle/10635/84076 |
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| Institution: | National University of Singapore |