Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory
10.1109/IEDM.2007.4418868
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| المؤلفون الرئيسيون: | , , , , , , , , |
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| مؤلفون آخرون: | |
| التنسيق: | Conference or Workshop Item |
| منشور في: |
2014
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| الوصول للمادة أونلاين: | http://scholarbank.nus.edu.sg/handle/10635/84323 |
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| المؤسسة: | National University of Singapore |
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sg-nus-scholar.10635-84323 |
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sg-nus-scholar.10635-843232024-11-10T18:36:36Z Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory Fu, J. Buddharaju, K.D. Teo, S.H.G. Zhu, C. Yu, M.B. Singh, N. Lo, G.Q. Balasubramanian, N. Kwong, D.L. ELECTRICAL & COMPUTER ENGINEERING 10.1109/IEDM.2007.4418868 Technical Digest - International Electron Devices Meeting, IEDM 79-82 TDIMD 2014-10-07T04:51:22Z 2014-10-07T04:51:22Z 2007 Conference Paper Fu, J., Buddharaju, K.D., Teo, S.H.G., Zhu, C., Yu, M.B., Singh, N., Lo, G.Q., Balasubramanian, N., Kwong, D.L. (2007). Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory. Technical Digest - International Electron Devices Meeting, IEDM : 79-82. ScholarBank@NUS Repository. https://doi.org/10.1109/IEDM.2007.4418868 01631918 http://scholarbank.nus.edu.sg/handle/10635/84323 000259347800016 Scopus |
| institution |
National University of Singapore |
| building |
NUS Library |
| continent |
Asia |
| country |
Singapore Singapore |
| content_provider |
NUS Library |
| collection |
ScholarBank@NUS |
| description |
10.1109/IEDM.2007.4418868 |
| author2 |
ELECTRICAL & COMPUTER ENGINEERING |
| author_facet |
ELECTRICAL & COMPUTER ENGINEERING Fu, J. Buddharaju, K.D. Teo, S.H.G. Zhu, C. Yu, M.B. Singh, N. Lo, G.Q. Balasubramanian, N. Kwong, D.L. |
| format |
Conference or Workshop Item |
| author |
Fu, J. Buddharaju, K.D. Teo, S.H.G. Zhu, C. Yu, M.B. Singh, N. Lo, G.Q. Balasubramanian, N. Kwong, D.L. |
| spellingShingle |
Fu, J. Buddharaju, K.D. Teo, S.H.G. Zhu, C. Yu, M.B. Singh, N. Lo, G.Q. Balasubramanian, N. Kwong, D.L. Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory |
| author_sort |
Fu, J. |
| title |
Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory |
| title_short |
Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory |
| title_full |
Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory |
| title_fullStr |
Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory |
| title_full_unstemmed |
Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory |
| title_sort |
trap layer engineered gate-all-around vertically stacked twin si -nanowire nonvolatile memory |
| publishDate |
2014 |
| url |
http://scholarbank.nus.edu.sg/handle/10635/84323 |
| _version_ |
1821231276070273024 |