Computing the soft error rate of a combinational logic circuit using parameterized descriptors

by Rao, R.R., Chopra, K., Blaauw, D.T., Sylvester, D.M.
Published 2016

Compact HSPICE model for IMOS device

by Lin, J., Toh, E.H., Shen, C., Sylvester, D., Heng, C.H., Samudra, G., Yeo, Y.C.
Published 2014

Device design and scalability of a double-gate tunneling field-effect transistor with silicon - germanium source

by Toh, E.-H., Wang, G.H., Chan, L., Sylvester, D., Heng, C.-H., Samudra, G.S., Yeo, Y.-C.
Published 2014

A complementary-I-MOS technology featuring SiGe channel and I-region for enhancement of impact-ionization, breakdown voltage, and performance

by Toh, E.-H., Wang, G.H., Chan, L., Lo, G.-Q., Sylvester, D., Heng, C.-H., Samudra, G., Yeo, Y.-C.
Published 2014

Impact ionization nanowire transistor with multiple-gates, silicon-germanium impact ionization region, and sub-5 mV/decade subtheshold swing

by Toh, E.-H., Wang, G.H., Zhu, M., Shen, C., Chan, L., Lo, G.-Q., Tung, C.-H., Sylvester, D., Heng, C.-H., Samudra, G., Yeo, Y.-C.
Published 2014