A 5-Bit 1.25GS/S 4.7mW delay-based pipelined ADC in 65nm CMOS

A 5-Bit 1.25GS/S 4.7mW delay-based pipelined ADC in 65nm CMOS

This paper presents a delay based pipeline (DBP) analog to digital converter (ADC) suitable for high speed and low power applications. Active sample and hold and residue amplifier used in conventional pipeline ADCs are replaced by an analog delay line. The analog delay line is implemented by time-in...

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Bibliographic Details
Main Authors: Mesgarani, A., Tekin, A., Ay, S. U., Fu, Haipeng, Yan, Mei, Yu, Hao
Other Authors: School of Electrical and Electronic Engineering
Format: Conference or Workshop Item
Language:English
Published: 2013
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
Online Access:https://hdl.handle.net/10356/100932
http://hdl.handle.net/10220/18235
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Institution: Nanyang Technological University
Language: English
Description
Summary:This paper presents a delay based pipeline (DBP) analog to digital converter (ADC) suitable for high speed and low power applications. Active sample and hold and residue amplifier used in conventional pipeline ADCs are replaced by an analog delay line. The analog delay line is implemented by time-interleaved sampling of the signal in each stage of the ADC. A novel multi-phase clock generator is introduced to generate ADC timing signals. A 5-bit, 1.25 GS/s DBP ADC is designed in 65nm CMOS process. Post-layout simulations confirm that the proposed ADC achieves a peak SNDR of 30.5dB while consuming 4.7mW from a single 1.2V power supply.

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