A 5-Bit 1.25GS/S 4.7mW delay-based pipelined ADC in 65nm CMOS

• Main Authors: Mesgarani, A., Tekin, A., Ay, S. U., Fu, Haipeng, Yan, Mei, Yu, Hao
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
• Online Access: https://hdl.handle.net/10356/100932; http://hdl.handle.net/10220/18235
• Institution: Nanyang Technological University

This paper presents a delay based pipeline (DBP) analog to digital converter (ADC) suitable for high speed and low power applications. Active sample and hold and residue amplifier used in conventional pipeline ADCs are replaced by an analog delay line. The analog delay line is implemented by time-in...