A 5-Bit 1.25GS/S 4.7mW delay-based pipelined ADC in 65nm CMOS
This paper presents a delay based pipeline (DBP) analog to digital converter (ADC) suitable for high speed and low power applications. Active sample and hold and residue amplifier used in conventional pipeline ADCs are replaced by an analog delay line. The analog delay line is implemented by time-in...
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sg-ntu-dr.10356-1009322020-03-07T13:24:50Z A 5-Bit 1.25GS/S 4.7mW delay-based pipelined ADC in 65nm CMOS Mesgarani, A. Tekin, A. Ay, S. U. Fu, Haipeng Yan, Mei Yu, Hao School of Electrical and Electronic Engineering IEEE International Symposium on Circuits and Systems (2013 : Beijing, China) Broadcom Corporations, Irvine, CA, USA Electrical and Computer Engineering, University of Idaho, Moscow, ID, USA DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems This paper presents a delay based pipeline (DBP) analog to digital converter (ADC) suitable for high speed and low power applications. Active sample and hold and residue amplifier used in conventional pipeline ADCs are replaced by an analog delay line. The analog delay line is implemented by time-interleaved sampling of the signal in each stage of the ADC. A novel multi-phase clock generator is introduced to generate ADC timing signals. A 5-bit, 1.25 GS/s DBP ADC is designed in 65nm CMOS process. Post-layout simulations confirm that the proposed ADC achieves a peak SNDR of 30.5dB while consuming 4.7mW from a single 1.2V power supply. Accepted version 2013-12-13T02:11:08Z 2019-12-06T20:31:01Z 2013-12-13T02:11:08Z 2019-12-06T20:31:01Z 2013 2013 Conference Paper Mesgarani, A., Fu, H.P., Yan, M., Tekin, A., Yu, H., & Ay, S. U. (2013). A 5-Bit 1.25GS/S 4.7mW delay-based pipelined ADC in 65nm CMOS. IEEE International Symposium on Circuits and Systems (ISCAS) 2013. https://hdl.handle.net/10356/100932 http://hdl.handle.net/10220/18235 10.1109/ISCAS.2013.6572267 en © 2013 IEEE. This is the author created version of a work that has been peer reviewed and accepted for publication by IEEE International Symposium on Circuits and Systems (ISCAS) 2013, IEEE . It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: http://dx.doi.org/10.1109/ISCAS.2013.6572267. 4p. application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems Mesgarani, A. Tekin, A. Ay, S. U. Fu, Haipeng Yan, Mei Yu, Hao A 5-Bit 1.25GS/S 4.7mW delay-based pipelined ADC in 65nm CMOS |
| description |
This paper presents a delay based pipeline (DBP) analog to digital converter (ADC) suitable for high speed and low power applications. Active sample and hold and residue amplifier used in conventional pipeline ADCs are replaced by an analog delay line. The analog delay line is implemented by time-interleaved sampling of the signal in each stage of the ADC. A novel multi-phase clock generator is introduced to generate ADC timing signals. A 5-bit, 1.25 GS/s DBP ADC is designed in 65nm CMOS process. Post-layout simulations confirm that the proposed ADC achieves a peak SNDR of 30.5dB while consuming 4.7mW from a single 1.2V power supply. |
| author2 |
School of Electrical and Electronic Engineering |
| author_facet |
School of Electrical and Electronic Engineering Mesgarani, A. Tekin, A. Ay, S. U. Fu, Haipeng Yan, Mei Yu, Hao |
| format |
Conference or Workshop Item |
| author |
Mesgarani, A. Tekin, A. Ay, S. U. Fu, Haipeng Yan, Mei Yu, Hao |
| author_sort |
Mesgarani, A. |
| title |
A 5-Bit 1.25GS/S 4.7mW delay-based pipelined ADC in 65nm CMOS |
| title_short |
A 5-Bit 1.25GS/S 4.7mW delay-based pipelined ADC in 65nm CMOS |
| title_full |
A 5-Bit 1.25GS/S 4.7mW delay-based pipelined ADC in 65nm CMOS |
| title_fullStr |
A 5-Bit 1.25GS/S 4.7mW delay-based pipelined ADC in 65nm CMOS |
| title_full_unstemmed |
A 5-Bit 1.25GS/S 4.7mW delay-based pipelined ADC in 65nm CMOS |
| title_sort |
5-bit 1.25gs/s 4.7mw delay-based pipelined adc in 65nm cmos |
| publishDate |
2013 |
| url |
https://hdl.handle.net/10356/100932 http://hdl.handle.net/10220/18235 |
| _version_ |
1681048130092531712 |