A new method for enhancing high- k /metal-gate stack performance and reliability for high- k last integration

• Main Authors: Yew, K. S., Tang, L. J., Ang, Diing Shenp
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/105749; http://hdl.handle.net/10220/17726; http://dx.doi.org/10.1109/LED.2012.2231394
• Institution: Nanyang Technological University

We show that multistep deposition cum two-step annealing, comprising an ultraviolet ozone (UVO) anneal followed by a low-temperature rapid thermal anneal (RTA), can significantly improve the performance and reliability of a 7.5-Å-equivalent-oxide-thickness (EOT) HfO2/TiN gate stack, comprising a 25-Å HfO2 on ~3 Å SiOx, i.e., prepared from direct HfO2 deposition onto an HF-last Si surface. The method yields approximately two orders of magnitude reduction in gate current density and approximately an order of magnitude longer time to breakdown, as compared with the as-deposited gate stack. The observed improvements may be attributed to the “repair” of oxygen-vacancy defects at the HfO2/Si interface and in the HfO2 bulk by the absorbed ozone, through thermal activation provided by the RTA step. The findings provide a promising means for realizing low-leakage and reliable sub-1-nm EOT HfO2/TiN stacks for high-k last integration.