Surface-electrode ion trap with ground structures for minimizing the dielectric loss in the Si substrate
The surface-electrode ion trap is one of the key devices in modern ion-trapping apparatus to host the ion qubits for quantum computing. Surface traps fabricated on the silicon substrate have the versatility for complex electrode fabrication with 3-D integration capability. However, Si-induced dielec...
Saved in:
Main Authors: | , , , , , , |
---|---|
Other Authors: | |
Format: | Article |
Language: | English |
Published: |
2021
|
Subjects: | |
Online Access: | https://hdl.handle.net/10356/148249 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
id |
sg-ntu-dr.10356-148249 |
---|---|
record_format |
dspace |
spelling |
sg-ntu-dr.10356-1482492021-04-21T02:37:49Z Surface-electrode ion trap with ground structures for minimizing the dielectric loss in the Si substrate Tao, Jing Li, Hong Yu Lim, Yu Dian Zhao, Peng Apriyana, Anak Agung Alit Guidoni, Luca Tan, Chuan Seng School of Electrical and Electronic Engineering Engineering::Electrical and electronic engineering::Semiconductors Qubit Trapped Ion The surface-electrode ion trap is one of the key devices in modern ion-trapping apparatus to host the ion qubits for quantum computing. Surface traps fabricated on the silicon substrate have the versatility for complex electrode fabrication with 3-D integration capability. However, Si-induced dielectric loss has to be considered in trap design, and a ground structure is being incorporated to mitigate this concern. In this article, surface-electrode ion trap is fabricated using the standard Cu back-end process on a 300-mm Si wafer platform. Several process novelties are demonstrated: 1) the use of electroplated Cu/Au layers using microfabrication techniques to form the surface electrodes; 2) the use of dry etching to form the fine-gap oxide trench between the electrodes for reducing the charge-induced stray electric field; 3) the use of Cu mesh ground structure to enhance the resonance performance of the trap; and 4) process optimization to minimize the undercut in Cu/Au electrodes. Promising electrical properties are obtained from the fabricated ion trap with a leakage current failure rate of < 10% on a 300-mm wafer. Two trap types designed with radio-frequency (RF) linewidth of 80 and $40~\mu \text{m}$ are evaluated for their resonance performance with and without the ground plane. By incorporating ground plane into the ion trap, the resonance performances are significantly improved with an output power increment of 11 and 13 dB and $Q$ factor increment of 2 and 6 for the corresponding trap types. Agency for Science, Technology and Research (A*STAR) Accepted version This work is supported by Agency for Science, Technology and Research (A*STAR) under Individual Research Grant #A1783c0004. 2021-04-21T02:37:49Z 2021-04-21T02:37:49Z 2020 Journal Article Tao, J., Li, H. Y., Lim, Y. D., Zhao, P., Apriyana, A. A. A., Guidoni, L. & Tan, C. S. (2020). Surface-electrode ion trap with ground structures for minimizing the dielectric loss in the Si substrate. IEEE Transactions On Components, Packaging and Manufacturing Technology, 10(4), 679-685. https://dx.doi.org/10.1109/TCPMT.2019.2958661 2156-3985 0000-0001-5058-7688 0000-0003-4188-997X 0000-0003-1250-9165 https://hdl.handle.net/10356/148249 10.1109/TCPMT.2019.2958661 2-s2.0-85082990356 4 10 679 685 en A1685b0005 IEEE Transactions on Components, Packaging and Manufacturing Technology © 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TCPMT.2019.2958661 application/pdf |
institution |
Nanyang Technological University |
building |
NTU Library |
continent |
Asia |
country |
Singapore Singapore |
content_provider |
NTU Library |
collection |
DR-NTU |
language |
English |
topic |
Engineering::Electrical and electronic engineering::Semiconductors Qubit Trapped Ion |
spellingShingle |
Engineering::Electrical and electronic engineering::Semiconductors Qubit Trapped Ion Tao, Jing Li, Hong Yu Lim, Yu Dian Zhao, Peng Apriyana, Anak Agung Alit Guidoni, Luca Tan, Chuan Seng Surface-electrode ion trap with ground structures for minimizing the dielectric loss in the Si substrate |
description |
The surface-electrode ion trap is one of the key devices in modern ion-trapping apparatus to host the ion qubits for quantum computing. Surface traps fabricated on the silicon substrate have the versatility for complex electrode fabrication with 3-D integration capability. However, Si-induced dielectric loss has to be considered in trap design, and a ground structure is being incorporated to mitigate this concern. In this article, surface-electrode ion trap is fabricated using the standard Cu back-end process on a 300-mm Si wafer platform. Several process novelties are demonstrated: 1) the use of electroplated Cu/Au layers using microfabrication techniques to form the surface electrodes; 2) the use of dry etching to form the fine-gap oxide trench between the electrodes for reducing the charge-induced stray electric field; 3) the use of Cu mesh ground structure to enhance the resonance performance of the trap; and 4) process optimization to minimize the undercut in Cu/Au electrodes. Promising electrical properties are obtained from the fabricated ion trap with a leakage current failure rate of < 10% on a 300-mm wafer. Two trap types designed with radio-frequency (RF) linewidth of 80 and $40~\mu \text{m}$ are evaluated for their resonance performance with and without the ground plane. By incorporating ground plane into the ion trap, the resonance performances are significantly improved with an output power increment of 11 and 13 dB and $Q$ factor increment of 2 and 6 for the corresponding trap types. |
author2 |
School of Electrical and Electronic Engineering |
author_facet |
School of Electrical and Electronic Engineering Tao, Jing Li, Hong Yu Lim, Yu Dian Zhao, Peng Apriyana, Anak Agung Alit Guidoni, Luca Tan, Chuan Seng |
format |
Article |
author |
Tao, Jing Li, Hong Yu Lim, Yu Dian Zhao, Peng Apriyana, Anak Agung Alit Guidoni, Luca Tan, Chuan Seng |
author_sort |
Tao, Jing |
title |
Surface-electrode ion trap with ground structures for minimizing the dielectric loss in the Si substrate |
title_short |
Surface-electrode ion trap with ground structures for minimizing the dielectric loss in the Si substrate |
title_full |
Surface-electrode ion trap with ground structures for minimizing the dielectric loss in the Si substrate |
title_fullStr |
Surface-electrode ion trap with ground structures for minimizing the dielectric loss in the Si substrate |
title_full_unstemmed |
Surface-electrode ion trap with ground structures for minimizing the dielectric loss in the Si substrate |
title_sort |
surface-electrode ion trap with ground structures for minimizing the dielectric loss in the si substrate |
publishDate |
2021 |
url |
https://hdl.handle.net/10356/148249 |
_version_ |
1698713692785344512 |