Nanoscale strained-Si/SiGe and double-gate MOSFET modeling

192 p.

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Bibliographic Details
Main Author:	Karthik Chandrasekaran
Other Authors:	Subhash Chander Ruatagi
Format:	Theses and Dissertations
Published:	2010
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Online Access:	https://hdl.handle.net/10356/39174
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Institution:	Nanyang Technological University

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spelling	sg-ntu-dr.10356-391742023-07-04T17:04:53Z Nanoscale strained-Si/SiGe and double-gate MOSFET modeling Karthik Chandrasekaran Subhash Chander Ruatagi Zhou Xing School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits 192 p. A new approach to modeling non-classical CMOS devices, such as strainedsilicon (s-Si) and double-gate (DG) MOSFETs, is presented. We have employed a unified regional, non-pinned surface-potential based modeling approach, which is consistent with the prior development for bulk-MOS formulations. The key idea is to develop unified models with the correct physics and boundary conditions built into them, so that there is a seamless transition of models among different device structures like bulk, DG, SOI, and strained silicon. Threshold-voltage models are derived for surfaceand buried-channel strained-silicon MOSFETs based on the 1-D Poisson equation. DOCTOR OF PHILOSOPHY (EEE) 2010-05-21T04:47:16Z 2010-05-21T04:47:16Z 2007 2007 Thesis Karthik, C. (2007). Nanoscale strained-Si/SiGe and double-gate MOSFET modeling. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/39174 10.32657/10356/39174 application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
topic	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Karthik Chandrasekaran Nanoscale strained-Si/SiGe and double-gate MOSFET modeling
description	192 p.
author2	Subhash Chander Ruatagi
author_facet	Subhash Chander Ruatagi Karthik Chandrasekaran
format	Theses and Dissertations
author	Karthik Chandrasekaran
author_sort	Karthik Chandrasekaran
title	Nanoscale strained-Si/SiGe and double-gate MOSFET modeling
title_short	Nanoscale strained-Si/SiGe and double-gate MOSFET modeling
title_full	Nanoscale strained-Si/SiGe and double-gate MOSFET modeling
title_fullStr	Nanoscale strained-Si/SiGe and double-gate MOSFET modeling
title_full_unstemmed	Nanoscale strained-Si/SiGe and double-gate MOSFET modeling
title_sort	nanoscale strained-si/sige and double-gate mosfet modeling
publishDate	2010
url	https://hdl.handle.net/10356/39174
_version_	1772826302151131136

Nanoscale strained-Si/SiGe and double-gate MOSFET modeling

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