Data path allocation with interconnection optimization in high-level synthesis
In this thesis, a layout area estimation model based on bit-sliced standard cell design style was established. In this model, the unit area is formulated as a function of the 2-input NAND gate equivalent, and the routing track requirement is estimated using a probabilistics model.
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| Format: | Theses and Dissertations |
| Published: |
2008
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| Online Access: | http://hdl.handle.net/10356/4073 |
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| Institution: | Nanyang Technological University |
| Summary: | In this thesis, a layout area estimation model based on bit-sliced standard cell design style was established. In this model, the unit area is formulated as a function of the 2-input NAND gate equivalent, and the routing track requirement is estimated using a probabilistics model. |
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