Data path allocation with interconnection optimization in high-level synthesis

In this thesis, a layout area estimation model based on bit-sliced standard cell design style was established. In this model, the unit area is formulated as a function of the 2-input NAND gate equivalent, and the routing track requirement is estimated using a probabilistics model.

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Bibliographic Details
Main Author:	Zhu, Hongwei.
Other Authors:	Jong, Ching Chuen
Format:	Theses and Dissertations
Published:	2008
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Online Access:	http://hdl.handle.net/10356/4073
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Institution:	Nanyang Technological University

id	sg-ntu-dr.10356-4073
record_format	dspace
spelling	sg-ntu-dr.10356-40732023-07-04T15:42:10Z Data path allocation with interconnection optimization in high-level synthesis Zhu, Hongwei. Jong, Ching Chuen School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits In this thesis, a layout area estimation model based on bit-sliced standard cell design style was established. In this model, the unit area is formulated as a function of the 2-input NAND gate equivalent, and the routing track requirement is estimated using a probabilistics model. Master of Engineering 2008-09-17T09:43:50Z 2008-09-17T09:43:50Z 2001 2001 Thesis http://hdl.handle.net/10356/4073 Nanyang Technological University application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
topic	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Zhu, Hongwei. Data path allocation with interconnection optimization in high-level synthesis
description	In this thesis, a layout area estimation model based on bit-sliced standard cell design style was established. In this model, the unit area is formulated as a function of the 2-input NAND gate equivalent, and the routing track requirement is estimated using a probabilistics model.
author2	Jong, Ching Chuen
author_facet	Jong, Ching Chuen Zhu, Hongwei.
format	Theses and Dissertations
author	Zhu, Hongwei.
author_sort	Zhu, Hongwei.
title	Data path allocation with interconnection optimization in high-level synthesis
title_short	Data path allocation with interconnection optimization in high-level synthesis
title_full	Data path allocation with interconnection optimization in high-level synthesis
title_fullStr	Data path allocation with interconnection optimization in high-level synthesis
title_full_unstemmed	Data path allocation with interconnection optimization in high-level synthesis
title_sort	data path allocation with interconnection optimization in high-level synthesis
publishDate	2008
url	http://hdl.handle.net/10356/4073
_version_	1772827812134125568

Data path allocation with interconnection optimization in high-level synthesis

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