Data path allocation with interconnection optimization in high-level synthesis

• Main Author: Zhu, Hongwei.
• Other Authors: Jong, Ching Chuen
• Format: Theses and Dissertations
• Published: 2008
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: http://hdl.handle.net/10356/4073
• Institution: Nanyang Technological University

In this thesis, a layout area estimation model based on bit-sliced standard cell design style was established. In this model, the unit area is formulated as a function of the 2-input NAND gate equivalent, and the routing track requirement is estimated using a probabilistics model.