Data path allocation with interconnection optimization in high-level synthesis

In this thesis, a layout area estimation model based on bit-sliced standard cell design style was established. In this model, the unit area is formulated as a function of the 2-input NAND gate equivalent, and the routing track requirement is estimated using a probabilistics model.

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書目詳細資料
主要作者: Zhu, Hongwei.
其他作者: Jong, Ching Chuen
格式: Theses and Dissertations
出版: 2008
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在線閱讀:http://hdl.handle.net/10356/4073
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