Low-voltage, low-power CMOS arithmetic circuits for energy efficient VLSI applications

Low-voltage, low-power CMOS arithmetic circuits for energy efficient VLSI applications

We present in this thesis several algorithms and designs, and their IC implementation of low-voltage, low-power CMOS arithmetic circuits for energy efficient VLSI applications. The design methodologies span from circuit level, architecture level to algorithm level.

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書目詳細資料
主要作者:	Gu, Jiangmin
其他作者:	Chang Chip Hong
格式:	Theses and Dissertations
出版:	2008
主題:	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits.
在線閱讀:	https://hdl.handle.net/10356/4315
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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