Cu metallization and dielectric removal for failure analysis of ICs

Although a defect may be well understood electrically in the recent years, capturing the anomaly into image remains necessary to verify the defect location. As technology further develops, ICs nowadays have more than one interconnect layer. Hence, it is necessary to first remove the overlying layers...

Full description

Saved in:
Bibliographic Details
Main Author: Siah, Yu Wen.
Other Authors: Gan Chee Lip
Format: Final Year Project
Language:English
Published: 2012
Subjects:
Online Access:http://hdl.handle.net/10356/48443
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: Nanyang Technological University
Language: English
id sg-ntu-dr.10356-48443
record_format dspace
spelling sg-ntu-dr.10356-484432023-03-04T15:42:23Z Cu metallization and dielectric removal for failure analysis of ICs Siah, Yu Wen. Gan Chee Lip School of Materials Science and Engineering DRNTU::Engineering::Materials::Microelectronics and semiconductor materials::Nanoelectronics and interconnects Although a defect may be well understood electrically in the recent years, capturing the anomaly into image remains necessary to verify the defect location. As technology further develops, ICs nowadays have more than one interconnect layer. Hence, it is necessary to first remove the overlying layers, otherwise viewing of the embedded defects would be impossible. However, in some cases, the removal of one layer can act as an in-situ decoration of another layer, masking the defect or removing the defect. Thus, it is important that the delayering (also known as parallel lapping) method only removes the unwanted layer. The main focus of this project is to study the side effect of deprocessing technique for 65 nm copper chip focusing on polishing methodology. There are two known issues with polishing and they are, inability to achieve a 100% success rate and edge effects which affect the overall planarity of the sample. Edge effect can be caused by several factors such as long polishing times, excessive application of pressure or force, improper usage of slurry with wrong type of polishing cloth, sample is being lowered too much into the polishing cloth. In the experiments, the polisher was set with two different polishing modes which include oscillation with rotation and oscillation only. The purpose is to find out which of the mode would give a lesser edge effect. Moreover, the effect of the polishing duration and force applied on the sample during polishing as well as the introduction of sacrificial layers will be investigated. Optical images of the Cu chip were captured during the delayering process and FIB was also used to quantify the thicknesses of the layer stacks for analysis. After analyzing the results obtained from the experiments, it was found that polishing the sample with oscillation mode only and adding sacrificial to samples do help in minimizing edge effect at long polishing times. Bachelor of Engineering (Materials Engineering) 2012-04-24T00:59:46Z 2012-04-24T00:59:46Z 2012 2012 Final Year Project (FYP) http://hdl.handle.net/10356/48443 en Nanyang Technological University 42 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Materials::Microelectronics and semiconductor materials::Nanoelectronics and interconnects
spellingShingle DRNTU::Engineering::Materials::Microelectronics and semiconductor materials::Nanoelectronics and interconnects
Siah, Yu Wen.
Cu metallization and dielectric removal for failure analysis of ICs
description Although a defect may be well understood electrically in the recent years, capturing the anomaly into image remains necessary to verify the defect location. As technology further develops, ICs nowadays have more than one interconnect layer. Hence, it is necessary to first remove the overlying layers, otherwise viewing of the embedded defects would be impossible. However, in some cases, the removal of one layer can act as an in-situ decoration of another layer, masking the defect or removing the defect. Thus, it is important that the delayering (also known as parallel lapping) method only removes the unwanted layer. The main focus of this project is to study the side effect of deprocessing technique for 65 nm copper chip focusing on polishing methodology. There are two known issues with polishing and they are, inability to achieve a 100% success rate and edge effects which affect the overall planarity of the sample. Edge effect can be caused by several factors such as long polishing times, excessive application of pressure or force, improper usage of slurry with wrong type of polishing cloth, sample is being lowered too much into the polishing cloth. In the experiments, the polisher was set with two different polishing modes which include oscillation with rotation and oscillation only. The purpose is to find out which of the mode would give a lesser edge effect. Moreover, the effect of the polishing duration and force applied on the sample during polishing as well as the introduction of sacrificial layers will be investigated. Optical images of the Cu chip were captured during the delayering process and FIB was also used to quantify the thicknesses of the layer stacks for analysis. After analyzing the results obtained from the experiments, it was found that polishing the sample with oscillation mode only and adding sacrificial to samples do help in minimizing edge effect at long polishing times.
author2 Gan Chee Lip
author_facet Gan Chee Lip
Siah, Yu Wen.
format Final Year Project
author Siah, Yu Wen.
author_sort Siah, Yu Wen.
title Cu metallization and dielectric removal for failure analysis of ICs
title_short Cu metallization and dielectric removal for failure analysis of ICs
title_full Cu metallization and dielectric removal for failure analysis of ICs
title_fullStr Cu metallization and dielectric removal for failure analysis of ICs
title_full_unstemmed Cu metallization and dielectric removal for failure analysis of ICs
title_sort cu metallization and dielectric removal for failure analysis of ics
publishDate 2012
url http://hdl.handle.net/10356/48443
_version_ 1759853524489863168