Process development of nanowires for off-chip interconnects

• 主要作者: Chong, Ser Choong.
• 其他作者: School of Materials Science & Engineering
• 格式: Theses and Dissertations
• 出版: 2008
• 主題: DRNTU::Engineering::Materials::Microelectronics and semiconductor materials::Nanoelectronics and interconnects
• 在線閱讀: http://hdl.handle.net/10356/5123
• 機構: Nanyang Technological University

Nickel nanowires with solder cap are successfully fabricated on the test chip with well defined location. The location of the nanowires on the test chip can be pre-determined by using patterned silicon dioxide as the protective layer. The developed fabrication process of nanowires can be easily adapted in conventional IC fabrication process. XRD analysis was done on the nickel nanowires and confirmed that the Ni nanowires are polycrystalline but with a well-preferred orientation along the [111] direction. The test chip with nanowires was attached successfully on the silicon substrate using non-conductive adhesive. Electrical measurement done on the assembled test chip with nanowires indicated that the resistance of the nano-interconnects (~ 7 ?) was higher as compared to solder interconnects (less than 1 ? for similar daisy chain structure). The incomplete filling of nanowires in the bond pad and also the low nano-pores density may be the reasons behind the high resistance value.