Process development of nanowires for off-chip interconnects

Nickel nanowires with solder cap are successfully fabricated on the test chip with well defined location. The location of the nanowires on the test chip can be pre-determined by using patterned silicon dioxide as the protective layer. The developed fabrication process of nanowires can be easily adap...

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Main Author: Chong, Ser Choong.
Other Authors: School of Materials Science & Engineering
Format: Theses and Dissertations
Published: 2008
Subjects:
Online Access:http://hdl.handle.net/10356/5123
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Institution: Nanyang Technological University
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spelling sg-ntu-dr.10356-51232023-03-04T16:31:17Z Process development of nanowires for off-chip interconnects Chong, Ser Choong. School of Materials Science & Engineering DRNTU::Engineering::Materials::Microelectronics and semiconductor materials::Nanoelectronics and interconnects Nickel nanowires with solder cap are successfully fabricated on the test chip with well defined location. The location of the nanowires on the test chip can be pre-determined by using patterned silicon dioxide as the protective layer. The developed fabrication process of nanowires can be easily adapted in conventional IC fabrication process. XRD analysis was done on the nickel nanowires and confirmed that the Ni nanowires are polycrystalline but with a well-preferred orientation along the [111] direction. The test chip with nanowires was attached successfully on the silicon substrate using non-conductive adhesive. Electrical measurement done on the assembled test chip with nanowires indicated that the resistance of the nano-interconnects (~ 7 ?) was higher as compared to solder interconnects (less than 1 ? for similar daisy chain structure). The incomplete filling of nanowires in the bond pad and also the low nano-pores density may be the reasons behind the high resistance value. Master of Engineering (SME) 2008-09-17T10:20:36Z 2008-09-17T10:20:36Z 2007 2007 Thesis http://hdl.handle.net/10356/5123 Nanyang Technological University 69 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
topic DRNTU::Engineering::Materials::Microelectronics and semiconductor materials::Nanoelectronics and interconnects
spellingShingle DRNTU::Engineering::Materials::Microelectronics and semiconductor materials::Nanoelectronics and interconnects
Chong, Ser Choong.
Process development of nanowires for off-chip interconnects
description Nickel nanowires with solder cap are successfully fabricated on the test chip with well defined location. The location of the nanowires on the test chip can be pre-determined by using patterned silicon dioxide as the protective layer. The developed fabrication process of nanowires can be easily adapted in conventional IC fabrication process. XRD analysis was done on the nickel nanowires and confirmed that the Ni nanowires are polycrystalline but with a well-preferred orientation along the [111] direction. The test chip with nanowires was attached successfully on the silicon substrate using non-conductive adhesive. Electrical measurement done on the assembled test chip with nanowires indicated that the resistance of the nano-interconnects (~ 7 ?) was higher as compared to solder interconnects (less than 1 ? for similar daisy chain structure). The incomplete filling of nanowires in the bond pad and also the low nano-pores density may be the reasons behind the high resistance value.
author2 School of Materials Science & Engineering
author_facet School of Materials Science & Engineering
Chong, Ser Choong.
format Theses and Dissertations
author Chong, Ser Choong.
author_sort Chong, Ser Choong.
title Process development of nanowires for off-chip interconnects
title_short Process development of nanowires for off-chip interconnects
title_full Process development of nanowires for off-chip interconnects
title_fullStr Process development of nanowires for off-chip interconnects
title_full_unstemmed Process development of nanowires for off-chip interconnects
title_sort process development of nanowires for off-chip interconnects
publishDate 2008
url http://hdl.handle.net/10356/5123
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