Process development of nanowires for off-chip interconnects
Nickel nanowires with solder cap are successfully fabricated on the test chip with well defined location. The location of the nanowires on the test chip can be pre-determined by using patterned silicon dioxide as the protective layer. The developed fabrication process of nanowires can be easily adap...
Saved in:
Main Author: | Chong, Ser Choong. |
---|---|
Other Authors: | School of Materials Science & Engineering |
Format: | Theses and Dissertations |
Published: |
2008
|
Subjects: | |
Online Access: | http://hdl.handle.net/10356/5123 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Similar Items
-
Investigating the electromigration reliability of copper interconnects
by: Shao, Wei
Published: (2010) -
Investigation of cure stresses in non-conductive adhesive interconnects
by: Yu, Hong
Published: (2010) -
Study of electromigration-induced voiding mechanisms in Cu interconnects
by: Anand Vishwanath Vairagar
Published: (2010) -
Study on diffusion barriers for multilevel interconnect in advanced semiconductor devices
by: Lim, Boon Kiat.
Published: (2008) -
Hydrostatic stress and hydrostatic stress gradients in passivated copper interconnects
by: Ang, Derrick, et al.
Published: (2011)