An investigation on flip chip underfill delamination

• Main Author: Lee, Bryan Sik Pong.
• Other Authors: School of Mechanical and Production Engineering
• Format: Theses and Dissertations
• Published: 2008
• Subjects: DRNTU::Engineering::Manufacturing
• Online Access: http://hdl.handle.net/10356/6106
• Institution: Nanyang Technological University

Flip chip technology provides advantages of shorter possible leads, lower inductance, higher frequency, better noise control, higher density, greater input / output (I/O), smaller device footprints, and lower profile comparably with conventional wire bond technology or face-up TAB technology. These advantages best supported with two of the fastest growing industry, telecommunication and mobile device, especially in the mobile electronic equipments like phone and hand held electronic organizer or laptop which require most of the advantage that flip chip can provide. Due to this increase in demand of flip chip, reliability of the package becomes more of a concern. The mismatches of coefficient of thermal expansion on different materials will most likely lead to fatigue crack of the package and function failure of the electronic package. Coefficient of thermal expansion difference between the silicon die and the board, the solder bumps and the die, and the difference between solder bumps and substrate causes high thermal stress on the solder bumps. Underfill is added in between the silicon and the FR4 board in order to reduce the thermal stress at the solder joint, and therefore to increase fatigue life of the solder bumps because of the global thermal expansion mismatch between the silicon chip and the FR-4 PCB.