Investigation of interconnect layout on CU/Low-K TDDB reliability

• Main Author: Ong, Ran Xing
• Other Authors: Gan Chee Lip
• Format: Theses and Dissertations
• Language: English
• Published: 2015
• Subjects: DRNTU::Engineering::Materials::Microelectronics and semiconductor materials
• Online Access: https://hdl.handle.net/10356/62521
• Institution: Nanyang Technological University

Traditionally, conventional test structures and standard voltage biasing is used for the accelerated TDDB testing. However, the standard layout and bias conditions used are not representative of the actual circuit. Hence, in this project the influence of layout and biasing of the test structure on T...