Investigation of interconnect layout on CU/Low-K TDDB reliability
Traditionally, conventional test structures and standard voltage biasing is used for the accelerated TDDB testing. However, the standard layout and bias conditions used are not representative of the actual circuit. Hence, in this project the influence of layout and biasing of the test structure on T...
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sg-ntu-dr.10356-625212023-03-04T16:36:36Z Investigation of interconnect layout on CU/Low-K TDDB reliability Ong, Ran Xing Gan Chee Lip School of Materials Science & Engineering DRNTU::Engineering::Materials::Microelectronics and semiconductor materials Traditionally, conventional test structures and standard voltage biasing is used for the accelerated TDDB testing. However, the standard layout and bias conditions used are not representative of the actual circuit. Hence, in this project the influence of layout and biasing of the test structure on TDDB lifetime is examined. First, the effect of area was examined. It was found that lifetime data gathered from small head-to-head geometries commonly seen in actual circuits cannot be extrapolated to large are conventional comb structures. Secondly, the effect of having adjacent metal lines in close proximity was studied. The interaction of the electric field between adjacent electrodes was found to lead to a decrease in the TDDB lifetime. Finally, the effect of electromigration (EM) in the metal line was investigated. Compressive stress induced by EM deforms the metal line, leading to reduction of the dielectric spacing, causing the TDDB to be shortened. DOCTOR OF PHILOSOPHY (MSE) 2015-04-14T06:34:28Z 2015-04-14T06:34:28Z 2015 2015 Thesis Ong, R. X. (2015). Investigation of interconnect layout on CU/Low-K TDDB reliability. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/62521 10.32657/10356/62521 en 143 p. application/pdf |
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DRNTU::Engineering::Materials::Microelectronics and semiconductor materials Ong, Ran Xing Investigation of interconnect layout on CU/Low-K TDDB reliability |
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Traditionally, conventional test structures and standard voltage biasing is used for the accelerated TDDB testing. However, the standard layout and bias conditions used are not representative of the actual circuit. Hence, in this project the influence of layout and biasing of the test structure on TDDB lifetime is examined. First, the effect of area was examined. It was found that lifetime data gathered from small head-to-head geometries commonly seen in actual circuits cannot be extrapolated to large are conventional comb structures. Secondly, the effect of having adjacent metal lines in close proximity was studied. The interaction of the electric field between adjacent electrodes was found to lead to a decrease in the TDDB lifetime. Finally, the effect of electromigration (EM) in the metal line was investigated. Compressive stress induced by EM deforms the metal line, leading to reduction of the dielectric spacing, causing the TDDB to be shortened. |
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Gan Chee Lip |
author_facet |
Gan Chee Lip Ong, Ran Xing |
format |
Theses and Dissertations |
author |
Ong, Ran Xing |
author_sort |
Ong, Ran Xing |
title |
Investigation of interconnect layout on CU/Low-K TDDB reliability |
title_short |
Investigation of interconnect layout on CU/Low-K TDDB reliability |
title_full |
Investigation of interconnect layout on CU/Low-K TDDB reliability |
title_fullStr |
Investigation of interconnect layout on CU/Low-K TDDB reliability |
title_full_unstemmed |
Investigation of interconnect layout on CU/Low-K TDDB reliability |
title_sort |
investigation of interconnect layout on cu/low-k tddb reliability |
publishDate |
2015 |
url |
https://hdl.handle.net/10356/62521 |
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1759853865671327744 |