Package and board level reliability modeling of advanced CSP pakages for telecommunication applications
Market for telecommunication products (e.g., mobile phones) is very competitive, demanding products which are more reliable, higher performance, lighter, smaller, cheaper, and shorter time-to-market. These technology requirements are possible with the recent development of advanced Chip Scale Packag...
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| Format: | Theses and Dissertations |
| Published: |
2008
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| Online Access: | https://hdl.handle.net/10356/6512 |
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| Institution: | Nanyang Technological University |
| Summary: | Market for telecommunication products (e.g., mobile phones) is very competitive, demanding products which are more reliable, higher performance, lighter, smaller, cheaper, and shorter time-to-market. These technology requirements are possible with the recent development of advanced Chip Scale Packages (CSPs), such as thin-profile fine-pitch Ball Grid Array (TFBGA), Quad-Flat-No-lead (QFN), and wafer-level CSP (WL-CSP). However, due to limited product development time, these CSPs are usually not tested and studied in detail before introduction to the market. As a result, the package design may not be optimized for various reliability requirements, e.g., popcorn, thermal cycling test, and drop test. |
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