Package and board level reliability modeling of advanced CSP pakages for telecommunication applications
Market for telecommunication products (e.g., mobile phones) is very competitive, demanding products which are more reliable, higher performance, lighter, smaller, cheaper, and shorter time-to-market. These technology requirements are possible with the recent development of advanced Chip Scale Packag...
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sg-ntu-dr.10356-65122023-03-11T17:45:52Z Package and board level reliability modeling of advanced CSP pakages for telecommunication applications Tee, Tong Yan Zhong Zhaowei School of Mechanical and Aerospace Engineering DRNTU::Engineering::Manufacturing::Product engineering Market for telecommunication products (e.g., mobile phones) is very competitive, demanding products which are more reliable, higher performance, lighter, smaller, cheaper, and shorter time-to-market. These technology requirements are possible with the recent development of advanced Chip Scale Packages (CSPs), such as thin-profile fine-pitch Ball Grid Array (TFBGA), Quad-Flat-No-lead (QFN), and wafer-level CSP (WL-CSP). However, due to limited product development time, these CSPs are usually not tested and studied in detail before introduction to the market. As a result, the package design may not be optimized for various reliability requirements, e.g., popcorn, thermal cycling test, and drop test. DOCTOR OF PHILOSOPHY (MAE) 2008-09-17T11:16:55Z 2008-09-17T11:16:55Z 2005 2005 Thesis Tee, T. Y. (2005). Package and board level reliability modeling of advanced CSP pakages for telecommunication applications. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/6512 10.32657/10356/6512 Nanyang Technological University application/pdf |
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DRNTU::Engineering::Manufacturing::Product engineering Tee, Tong Yan Package and board level reliability modeling of advanced CSP pakages for telecommunication applications |
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Market for telecommunication products (e.g., mobile phones) is very competitive, demanding products which are more reliable, higher performance, lighter, smaller, cheaper, and shorter time-to-market. These technology requirements are possible with the recent development of advanced Chip Scale Packages (CSPs), such as thin-profile fine-pitch Ball Grid Array (TFBGA), Quad-Flat-No-lead (QFN), and wafer-level CSP (WL-CSP). However, due to limited product development time, these CSPs are usually not tested and studied in detail before introduction to the market. As a result, the package design may not be optimized for various reliability requirements, e.g., popcorn, thermal cycling test, and drop test. |
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Zhong Zhaowei |
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Zhong Zhaowei Tee, Tong Yan |
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Theses and Dissertations |
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Tee, Tong Yan |
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Tee, Tong Yan |
title |
Package and board level reliability modeling of advanced CSP pakages for telecommunication applications |
title_short |
Package and board level reliability modeling of advanced CSP pakages for telecommunication applications |
title_full |
Package and board level reliability modeling of advanced CSP pakages for telecommunication applications |
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Package and board level reliability modeling of advanced CSP pakages for telecommunication applications |
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Package and board level reliability modeling of advanced CSP pakages for telecommunication applications |
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package and board level reliability modeling of advanced csp pakages for telecommunication applications |
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2008 |
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https://hdl.handle.net/10356/6512 |
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1761782081000570880 |