Design methodologies for robust and low-overhead asynchronous quasi-delay-insensitive digital systems
In the past decades of electronic circuit designs, the synchronous-logic (sync) is the main de-facto design approach for digital systems. This is largely due to its synchronization to a global clock signal (or its variants thereof) which simplifies the data transfer. Nevertheless, designing digital...
Saved in:
Main Author: | Zhou, Rong |
---|---|
Other Authors: | Gwee Bah Hwee |
Format: | Theses and Dissertations |
Language: | English |
Published: |
2015
|
Subjects: | |
Online Access: | https://hdl.handle.net/10356/65411 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
Design of ultra-low power asynchronous-logic quasi-delay-insensitive circuit templates
by: Chng, Clive Kuan Nee.
Published: (2011) -
Design of asynchronous quasi-delay-insensitive library cells and circuits for asynchronous microprocessors
by: Chin, Qi Lin.
Published: (2009) -
Ultra low power asynchronous-logic quasi-delay-insensitive circuit design
by: Ho, Weng Geng
Published: (2016) -
A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA)
by: Zhou, Rong, et al.
Published: (2015) -
Quasi-delay-insensitive implementation of approximate addition
by: Balasubramanian, Padmanabhan, et al.
Published: (2021)