Bimodal weibull distribution of metal/high-κ gate stack TDDB-insights by scanning tunneling microscopy

• Main Authors: Yew, K. S., Bersuker, G., Ang, Diing Shenp
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/85052; http://hdl.handle.net/10220/11337
• Institution: Nanyang Technological University

We provide new insights, via nanoscale TDDB testing, into the bimodal Weibull failure distribution obtained from area scaling of high-κ (HK) gate stack. Time-to-breakdown (BD) statistics for grain boundary (GB) and grain in a polycrystalline HK gate stack are obtained individually from localized constant voltage stressing via a scanning tunneling microscope. In spite of an initial difference in the preexisting defect density, no apparent difference in the Weibull slope is observed for the two sets of BD statistics. The bimodal Weibull distribution is shown to be a combined effect: 1) The steep Weibull slope of the lower percentile, arising from large-area devices, is related to BD at GBs, and 2) the upper percentile, arising from small-area devices, is mostly related to grain BDs. In this case, the Weibull slope is reduced by a small fraction of these devices exhibiting early failures due to GB BDs. We show directly that structural defects in an HK dielectric, particularly GBs, play an important role on its BD distribution.