Through silicon via fabrication with low-κ dielectric liner and its implications on parasitic capacitance and leakage current

• Main Authors: Zhang, Lin, Lim, Dau Fatt, Li, Hong Yu, Gao, Shan, Tan, Chuan Seng
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/96978; http://hdl.handle.net/10220/11653
• Institution: Nanyang Technological University

Through silicon via (TSV) has emerged as an essential enabler for three-dimensional integrated circuit (3D IC). The basic TSV structure consisting of a via hole in the Si substrate filled with metal such as copper and lined with a dielectric liner, forms a metal–oxide–silicon (MOS) capacitor structu...