Strategy for TSV scaling with consideration on thermo-mechanical stress and acceptable delay

Strategy for TSV scaling with consideration on thermo-mechanical stress and acceptable delay

Based on the 2011 ITRS road map, the greater accessibility of higher number of TSVs in a specified area depends on the smarter miniaturization of the interconnect dimension in 3D IC packaging. Scaling down the TSV dimension has an inevitable effect on resistance, capacitance, signal transmission as...

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Bibliographic Details
Main Authors: Zhang, J., Zhang, L., Dong, Y., Li, H. Y., Ghosh, Kaushik, Tan, Cher Ming, Xia, Guangrui, Tan, Chuan Seng
Other Authors: School of Electrical and Electronic Engineering
Format: Conference or Workshop Item
Language:English
Published: 2013
Online Access:https://hdl.handle.net/10356/98846
http://hdl.handle.net/10220/12742
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Institution: Nanyang Technological University
Language: English
Description
Summary:Based on the 2011 ITRS road map, the greater accessibility of higher number of TSVs in a specified area depends on the smarter miniaturization of the interconnect dimension in 3D IC packaging. Scaling down the TSV dimension has an inevitable effect on resistance, capacitance, signal transmission as well as the thermo-mechanical stress. We report that the lowering of the TSV diameter is permissible under thermo-mechanical stress consideration. However, the signal transmission delay explodes rapidly and could be tunable via controlling the liner layer capacitance or/and using alternative filler materials.

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