Strategy for TSV scaling with consideration on thermo-mechanical stress and acceptable delay

Based on the 2011 ITRS road map, the greater accessibility of higher number of TSVs in a specified area depends on the smarter miniaturization of the interconnect dimension in 3D IC packaging. Scaling down the TSV dimension has an inevitable effect on resistance, capacitance, signal transmission as...

وصف كامل

محفوظ في:
التفاصيل البيبلوغرافية
المؤلفون الرئيسيون: Zhang, J., Zhang, L., Dong, Y., Li, H. Y., Ghosh, Kaushik, Tan, Cher Ming, Xia, Guangrui, Tan, Chuan Seng
مؤلفون آخرون: School of Electrical and Electronic Engineering
التنسيق: Conference or Workshop Item
اللغة:English
منشور في: 2013
الوصول للمادة أونلاين:https://hdl.handle.net/10356/98846
http://hdl.handle.net/10220/12742
الوسوم: إضافة وسم
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المؤسسة: Nanyang Technological University
اللغة: English
الوصف
الملخص:Based on the 2011 ITRS road map, the greater accessibility of higher number of TSVs in a specified area depends on the smarter miniaturization of the interconnect dimension in 3D IC packaging. Scaling down the TSV dimension has an inevitable effect on resistance, capacitance, signal transmission as well as the thermo-mechanical stress. We report that the lowering of the TSV diameter is permissible under thermo-mechanical stress consideration. However, the signal transmission delay explodes rapidly and could be tunable via controlling the liner layer capacitance or/and using alternative filler materials.