Strategy for TSV scaling with consideration on thermo-mechanical stress and acceptable delay
Based on the 2011 ITRS road map, the greater accessibility of higher number of TSVs in a specified area depends on the smarter miniaturization of the interconnect dimension in 3D IC packaging. Scaling down the TSV dimension has an inevitable effect on resistance, capacitance, signal transmission as...
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| Main Authors: | , , , , , , , |
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| 其他作者: | |
| 格式: | Conference or Workshop Item |
| 語言: | English |
| 出版: |
2013
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| 在線閱讀: | https://hdl.handle.net/10356/98846 http://hdl.handle.net/10220/12742 |
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| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | Based on the 2011 ITRS road map, the greater accessibility of higher number of TSVs in a specified area depends on the smarter miniaturization of the interconnect dimension in 3D IC packaging. Scaling down the TSV dimension has an inevitable effect on resistance, capacitance, signal transmission as well as the thermo-mechanical stress. We report that the lowering of the TSV diameter is permissible under thermo-mechanical stress consideration. However, the signal transmission delay explodes rapidly and could be tunable via controlling the liner layer capacitance or/and using alternative filler materials. |
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