Strategy for TSV scaling with consideration on thermo-mechanical stress and acceptable delay
Based on the 2011 ITRS road map, the greater accessibility of higher number of TSVs in a specified area depends on the smarter miniaturization of the interconnect dimension in 3D IC packaging. Scaling down the TSV dimension has an inevitable effect on resistance, capacitance, signal transmission as...
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sg-ntu-dr.10356-988462020-03-07T13:24:49Z Strategy for TSV scaling with consideration on thermo-mechanical stress and acceptable delay Zhang, J. Zhang, L. Dong, Y. Li, H. Y. Ghosh, Kaushik Tan, Cher Ming Xia, Guangrui Tan, Chuan Seng School of Electrical and Electronic Engineering International Microsystems, Packaging, Assembly and Circuits Technology Conference (7th : 2012 : Taipei, Taiwan) Based on the 2011 ITRS road map, the greater accessibility of higher number of TSVs in a specified area depends on the smarter miniaturization of the interconnect dimension in 3D IC packaging. Scaling down the TSV dimension has an inevitable effect on resistance, capacitance, signal transmission as well as the thermo-mechanical stress. We report that the lowering of the TSV diameter is permissible under thermo-mechanical stress consideration. However, the signal transmission delay explodes rapidly and could be tunable via controlling the liner layer capacitance or/and using alternative filler materials. 2013-08-01T03:31:33Z 2019-12-06T20:00:15Z 2013-08-01T03:31:33Z 2019-12-06T20:00:15Z 2012 2012 Conference Paper Ghosh, K., Zhang, J., Zhang, L., Dong, Y., Li, H., Tan, C. M., Xia, G., & Tan, C. S. (2012). Strategy for TSV scaling with consideration on thermo-mechanical stress and acceptable delay. 2012 7th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 49 - 51. https://hdl.handle.net/10356/98846 http://hdl.handle.net/10220/12742 10.1109/IMPACT.2012.6420220 en |
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Based on the 2011 ITRS road map, the greater accessibility of higher number of TSVs in a specified area depends on the smarter miniaturization of the interconnect dimension in 3D IC packaging. Scaling down the TSV dimension has an inevitable effect on resistance, capacitance, signal transmission as well as the thermo-mechanical stress. We report that the lowering of the TSV diameter is permissible under thermo-mechanical stress consideration. However, the signal transmission delay explodes rapidly and could be tunable via controlling the liner layer capacitance or/and using alternative filler materials. |
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School of Electrical and Electronic Engineering |
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School of Electrical and Electronic Engineering Zhang, J. Zhang, L. Dong, Y. Li, H. Y. Ghosh, Kaushik Tan, Cher Ming Xia, Guangrui Tan, Chuan Seng |
format |
Conference or Workshop Item |
author |
Zhang, J. Zhang, L. Dong, Y. Li, H. Y. Ghosh, Kaushik Tan, Cher Ming Xia, Guangrui Tan, Chuan Seng |
spellingShingle |
Zhang, J. Zhang, L. Dong, Y. Li, H. Y. Ghosh, Kaushik Tan, Cher Ming Xia, Guangrui Tan, Chuan Seng Strategy for TSV scaling with consideration on thermo-mechanical stress and acceptable delay |
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Zhang, J. |
title |
Strategy for TSV scaling with consideration on thermo-mechanical stress and acceptable delay |
title_short |
Strategy for TSV scaling with consideration on thermo-mechanical stress and acceptable delay |
title_full |
Strategy for TSV scaling with consideration on thermo-mechanical stress and acceptable delay |
title_fullStr |
Strategy for TSV scaling with consideration on thermo-mechanical stress and acceptable delay |
title_full_unstemmed |
Strategy for TSV scaling with consideration on thermo-mechanical stress and acceptable delay |
title_sort |
strategy for tsv scaling with consideration on thermo-mechanical stress and acceptable delay |
publishDate |
2013 |
url |
https://hdl.handle.net/10356/98846 http://hdl.handle.net/10220/12742 |
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1681034313016016896 |