Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit
In dual-loops clock and data recovery (CDR) circuit design, lock detector is crucial in controlling the switching within CDR loop. The setting of the frequency accuracy of lock detector is a tough task as large ppm will leads to a longer lock time for phase tracking loop and small ppm will lead...
Saved in:
| Main Authors: | , , , |
|---|---|
| 其他作者: | |
| 格式: | Conference or Workshop Item |
| 語言: | English |
| 出版: |
2013
|
| 主題: | |
| 在線閱讀: | https://hdl.handle.net/10356/99816 http://hdl.handle.net/10220/17712 |
| 標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|
| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | In dual-loops clock and data recovery (CDR)
circuit design, lock detector is crucial in controlling the
switching within CDR loop. The setting of the frequency
accuracy of lock detector is a tough task as large ppm will
leads to a longer lock time for phase tracking loop and small
ppm will leads to more switching time between the loops. A
novel lock detector with hysteresis property is proposed in
this paper. It provides two different ppms in both different
conditions; a smaller ppm for in-lock condition and a larger
ppm for out-of-lock condition. This paper also provides a
detailed analysis of the proposed lock detector at different
conditions. The proposed lock detector is simulated in 0.18-
um technology and it consumes 1.1-mW at a 1.8V supply
voltage. |
|---|