Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit

In dual-loops clock and data recovery (CDR) circuit design, lock detector is crucial in controlling the switching within CDR loop. The setting of the frequency accuracy of lock detector is a tough task as large ppm will leads to a longer lock time for phase tracking loop and small ppm will lead...

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Bibliographic Details
Main Authors: Tan, Yung Sern, Yeo, Kiat Seng, Boon, Chirn Chye, Do, Manh Anh
Other Authors: School of Electrical and Electronic Engineering
Format: Conference or Workshop Item
Language:English
Published: 2013
Subjects:
Online Access:https://hdl.handle.net/10356/99816
http://hdl.handle.net/10220/17712
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Institution: Nanyang Technological University
Language: English

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